Design and Implementation of Cache Memory on VHDL
Expertise: Computer System Architecture, VLSI Design
Outcome: Synthesizable VHDL, Functional and Timing Simulation Report.
Design and Implementation of Two-Way Set Associative Cache using VHDL
Bagus Hanindhito1, Audra Fildza Masita2
Department of Electrical Engineering, School of Electrical Engineering and Informatics
Institut Teknologi Bandung, Indonesia
Email : firstname.lastname@example.org, email@example.com
Abstract—Cache memory is an important small but fast temporary storage for CPU. It stores frequently used data for current execution in CPU. Because accessing data directly from main memory will gives significant penalty for CPU performance, having a cache memory brings a lot of reduction in average data access cost. With its smaller capacity, cache has its own structures and replacement algorithm to reduce cache miss, that is the data needed by CPU is not available in cache thus they must be taken from main memory. Usually, a CPU has separated instruction cache and data cache. The data cache can consist of two or more levels which determines its size and its proximity to the processor.
In this project, a two-way set associative cache is implemented in a synthesizable VHDL. The cache has 16-bit address, 8 sets, 8 byte data block, and random replacement algorithm. The random replacement is obtained from Linear Feedback Shift Register. The cache will also output whether the requested data available on cache (cache hit) or not (cache miss).
Index Terms— Cache Memory, two-way set associative, VHDL