Design and Implementation of Single-Cycle, Multi-Cycle and Pipeline architecture of MIPS microprocessor using VHDL

Bagus Hanindhito¹, Audra Fildza Masita²
Department of Electrical Engineering, School of Electrical Engineering and Informatics
Institut Teknologi Bandung, Indonesia
Email : ¹hanindhito@bagus.my.id, ²afmasita@gmail.com

Abstract—MIPS (Microprocessor without Interlocked Pipeline Stages) is a microprocessor architecture developed by MIPS Technologies. Its instruction set architecture design is based on reduced instruction set computer (RISC) architecture. It has 32 general purpose registers, including an always-zero register, and 32 floating point registers. It can only perform arithmetic and logical operations in its registers. In this project, three designs of MIPS microprocessor are implemented in a synthesizable VHDL. The MIPS can execute eight basic instructions and one “no operation” instruction.

First, a single-cycle MIPS is implemented. MIPS architecture consists of five stages: Instruction Fetch (IF), Instruction Decode (ID), Execute / Address Calculation (EX), Data Memory Access (MEM), and Write Back (WB). In single cycle design, each instruction will go through all of the stages regardless of whether a stage is needed or not. Moreover, all of the five stages will have been done in one clock cycle only, making the clock has a long period. Although it seems inefficient, the single cycle design is the simplest design in this project.

Furthermore, the single-cycle design is modified into multi-cycle design. This modification is carried out by adding some buffers in between each stage. The buffers make a stage must be done in one clock cycle thus all of the stages will be done in five clock cycles. Hence it is named multi-cycle. This multi-cycle design brings oportunity to execute instructions efficiently. For example, branch instruction will only need three clock cycles thus it does not need to go through the end of stages. It will save the precious time to execute next instruction. Moreover, the clock period is now shorter than the single-cycle design, giving the possibility to run the microprocessor at higher clock speed.

Lastly, the multi-cycle design is modified into pipelined design. The pipelined-design offers more performance and efficiency with a cost of more complex circuits. With pipeline-design, one clock cycle can execute up-to five instructions together assumming the pipeline is full. For example, as an instruction goes through the second stage, the next instruction does not need to wait until the first instruction finishes its full cycle. Instead, it will enter the currently empty first stage. To make it works, more complex circuits need to be added: hazard detection and handler, and branch prediction.

Index Terms— MIPS, Multi-Cycle, Pipeline, Single-Cycle.